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3D7521
MONOLITHIC MANCHESTER ENCODER (SERIES 3D7521)
FEATURES
* * * * * All-silicon, low-power CMOS technology TTL/CMOS compatible inputs and outputs Vapor phase, IR and wave solderable Low ground bounce noise Maximum data rate: 50 MBaud
data 3 delay devices, inc.
PACKAGES
CLK N/C N/C 1 2 3 4 5 6 7 14 13 12 11 10 9 8
VDD N/C N/C N/C N/C TXB TX
CLK RESB DAT GND 3D7521Z
1 2 3 4
8 7 6 5
VDD N/C TXB TX
RESB DAT N/C GND
SOIC (.150)
3D7521D SOIC (.150)
For mechanical dimensions, click here. For package marking details, click here.
FUNCTIONAL DESCRIPTION
The 3D7521 is a monolithic CMOS Manchester Encoder. The clock and data, present at the unit input, are combined into a single bi-phaselevel signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is represented by a low-to-high transition. The unit operating baud rate (in Mbaud) is equal to the input clock frequency (in MHZ). All pins marked N/C must be left unconnected.
PIN DESCRIPTIONS
DAT CLK RESB TX TXB VDD GND Data Input Clock Input Reset Signal Output Inverted Signal Output +5 Volts Ground
The all-CMOS 3D7521 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL Manchester Encoder. It is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads. It is offered in space saving surface mount 8-pin and 14-pin SOICs.
Doc #06001
10/31/2007
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D7521
APPLICATION NOTES
The 3D7521 Manchester Encoder samples the data input at the rising edge of the input clock. The sampled data is used in conjunction with the clock rising and falling edges to generate the byphase level Manchester code.
OUTPUT SIGNAL CHARACTERISTICS
The 3D7521 presents at its outputs the true and the complimented encoded data. The High-to-Low time skew of the selected data output should be budgeted by the user, as it relates to his application, to satisfactorily estimate the distortion of the transmitted data stream. Such an estimate is very useful in determining the functionality and margins of the data link, if a 3D7522 Manchester Decoder is used to decode the received data.
INPUT SIGNAL CHARACTERISTICS
The 3D7521 Manchester Encoder inputs are TTL compatible. The user should assure himself that the 1.5 volt TTL threshold is used when referring to all timing, especially to the input clock duty cycle.
CLOCK DUTY CYCLE ERRORS
The 3D7521 Manchester Encoder employs the timing of the clock rising and falling edges (duty cycle) to implement the required coding scheme. To reduce the difference between the output data high time and low time, it is essential that the deviation of the input clock duty cycle from 50/50 be minimized.
POWER SUPPLY AND TEMPERATURE CONSIDERATIONS
CMOS integrated circuitry is strongly dependent on power supply and temperature. The monolithic 3D7521 Manchester encoder utilizes novel and innovative compensation circuitry to minimize timing variations induced by fluctuations in power supply and/or temperature.
RESET (RESB)
Power-on reset (Left high for normal operation)
1/fC 1 0 1 1 0 0 1 0
CLOCK (CIN)
tDS
DATA (DIN)
tDH T2H T2L T1H T1L
TRANSMIT (TXB) TRANSMIT (TX)
1
0
1
1
0
0
1
0
Figure 1: Timing Diagram
Doc #06001
10/31/2007
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
3D7521
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN -0.3 -0.3 -10 -55 MAX 7.0 VDD+0.3 10 150 300 UNITS V V mA C C NOTES
25C 10 sec
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current Low Level Output Current Output Rise & Fall Time SYMBOL IDD VIH VIL IIH IIL IOH IOL TR & TF MIN 2.0 0.8 1.0 1.0 -4.0 4.0 2 MAX 5 UNITS mA V V A A mA mA ns NOTES
VIH = VDD VIL = 0V VDD = 4.75V VOH = 2.4V VDD = 4.75V VOL = 0.4V CLD = 5 pf
*IDD(Dynamic) = 2 * CLD * VDD * F where: CLD = Average capacitance load/pin (pf) F = Input frequency (GHz)
Input Capacitance = 10 pf typical Output Load Capacitance (CLD) = 25 pf max
TABLE 3: AC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V) PARAMETER Input Baud Rate Clock Frequency Data set-up to clock rising Data hold from clock rising TX High-Low time skew TXB High-Low time skew TX - TXB High/Low time skew
SYMBOL
MIN
TYP
fBN fC tDS tDH t1H - t1L t2H - t2L t1H - t2L
MAX 50 50
3.5 0 -3.5 -2.0 -3.0
3.5 2.0 3.0
UNITS MBaud MHz ns ns ns ns ns
NOTES
1 1 1
Notes: 1: Assumes a 50% duty cycle clock input
Doc #06001
10/31/2007
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3D7521
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC 3oC Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High = 3.0V 0.1V Low = 0.0V 0.1V Source Impedance: 50 Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width: PWIN = 1/(2*BAUD) Period: PERIN = 1/BAUD OUTPUT: Rload: Cload: Threshold: 10K 10% 5pf 10% 1.5V (Rising & Falling)
Device Under Test
10K 5pf
Digital Scope
470
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
COMPUTER SYSTEM
PRINTER
WAVEFORM GENERATOR
OUT TRIG
IN
DEVICE UNDER TEST (DUT)
OUT
IN TRIG
DIGITAL SCOPE
Figure 2: Test Setup
PERIN PW IN tRISE INPUT SIGNAL
2.4V 1.5V 0.6V
tFALL VIH
2.4V 1.5V 0.6V
VIL tPHL
tPLH OUTPUT SIGNAL
1.5V
VOH
1.5V
VOL
Figure 3: Timing Diagram
Doc #06001
10/31/2007
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
4

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